1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having an insulated gate transistor of a recess gate type (called hereinafter “recess gate transistor” or “recess channel transistor”).
2. Description of the Related Art
With the miniaturization of DRAM (dynamic random access memory) cells, recess gate transistors (recess channel transistors) have been invented to suppress the short channel effect of access transistors in a cell array (hereinafter, “cell transistors”) (see, for example, J. Y. KIM et al., Symp. on VLSI Tech., p 11-12, 2003).
As shown in FIG. 5, in a semiconductor device H1 with a recess-gate transistor structure, one or more recess gate transistors are formed in an active region defined by a shallow trench isolation (STI) region 102.
Specifically, an N-type diffusion layer 113 which will be a source and/or a drain (S/D) is formed on a surface of a semiconductor substrate 101 including a P-type channel doped layer 109. Recesses 106 are formed on the semiconductor substrate 101 and the N-type diffusion layer 113. Source regions and drain regions of the N-type diffusion layer 113 are separated from one another by the recesses 106. A gate insulating film 107 is formed on an inner surface of each recess 106. Agate electrode 112 is buried onto each recess 106. The channel doped layer 109 is formed around the bottom portions of the recesses 106 and the side surfaces of the bottom portions.
The gate electrode 112 includes a DOPOS film 108, a tungsten film 110, and a gate nitride film 111. The DOPOS film 108 is partially buried onto the recess 106 through the gate insulating film 107. In this manner, the gate electrode 112 is formed between the source and the drain regions of the N-type diffusion layer 113 through the gate insulating film 107.
An inter-layer insulating film 115 is formed on the gate electrode 112. Cell contact poly-plugs 117 are formed on the N-type diffusion layer 113 between the gate electrodes 112 through gate-sidewall nitride films 114.
Thus, the gate electrode 112 is buried onto the recess 106. Thereby, an effective channel length can be controlled by the depth of the recess, and a higher threshold voltage Vth can be obtained compared with conventional planar semiconductor devices.
Methods of manufacturing a semiconductor device having the recess gate transistor structure are disclosed in, for example, Japanese Laid-open Patent Publication Nos. H06-5798, H08-78682, and H10-50992.
Typical processes are explained. As shown in FIG. 6A, the element isolation regions 102 are formed on the P-type semiconductor substrate 101 using the STI (shallow trench isolation) technique. Then, a pad oxide film, a nitride film, and a photoresist film (not shown) are formed on the semiconductor substrate 101. After the photoresist film is patterned by lithography so as to have openings at substantially the same positions as those of the gate electrodes 112, the nitride film is formed by dry etching.
After the photoresist film is removed, the semiconductor device 101 is etched with the nitride film as a mask to form the recesses 106. Then, the nitride film and the pad oxide film are removed, and the gate insulating film 107 is formed on the semiconductor substrate 101 and the inner surfaces of the recesses 106.
Then, the DOPOS film 108 as a gate electrode material is formed on the semiconductor substrate 101 and inside the recesses 106. Then, a non-depicted photoresist pattern having openings at the positions corresponding to those of memory cell regions is formed by lithography. In this state, an impurity, such as boron, is ion-implanted through the DOPOS film 108 to form the P-type channel doped layer 109 around the bottom portions of the recesses 106.
Then, the tungsten film 110 is formed by CVD or spattering as shown in FIG. 6B. Then, the gate nitride film (SiN film) 111 is formed by low pressure CVD. Then, a photoresist film (not shown) is formed by lithography so as to match the recesses 106.
Then, the gate nitride film 111, the tungsten film 110, and the DOPOS film 108 are sequentially etched by dry etching to form the gate electrode 112 as shown in FIG. 6C. In this state, a photoresist pattern having openings at the positions corresponding to those of the memory cell regions is formed, and an impurity, such as phosphorus, is implanted so as to be doped only into the cell portions to form the N-type diffusion layer 113.
Then, the gate-sidewall nitride film 114 is formed. Then, the inter-layer insulating film 115 is formed. Then, contact holes 116 are formed on the inter-layer insulating film 115 by lithography and dry etching so that the source and drain regions (the N-type diffusion layer 113) are exposed. The cell-contact poly plugs 117 are formed by DOPOS film formation and polysilicon CMP. Thereby, the semiconductor device H1, as shown in FIG. 5, is completed.